We have a rising edge again, the D pin is low.

我们再次出现上升沿，D 引脚为低电平。

So we can see here at the time of the rising edge, D is on a high level.

所以我们可以看到这里在上升沿的时候，D处于高电平。

This is similar, but after the rising clock edge.

这很相似，但在时钟上升沿之后。

That D flip-flop is used to save data on every rising edge on this clock pin.

该 D 触发器用于在此时钟引脚上的每个上升沿保存数据。

So what happens is you have an input, the clock goes to the rising edge for sake of simplicity.

所以发生的是你有一个输入，为了简单起见，时钟进入上升沿。

And as I said, this flip-flop is edge triggered, which means every time we have a rising edge here in the clock, something will happen down here.

正如我所说，这个触发器是边沿触发的，这意味着每当我们在时钟中有一个上升沿时，这里就会发生一些事情。

And if we look at the D pin, these shaded areas here mean that it doesn't matter what this D pin is because the flip-flop will only act on a rising edge of the clock.

如果我们看一下 D 引脚，这里的这些阴影区域意味着这个 D 引脚是什么并不重要，因为触发器只会在时钟的上升沿起作用。

And every time there is a rising edge on that clock pin, the data is moved, whatever the bit is, zero or one, is moved to the Q output and the Q bar output.

每当该时钟引脚上出现上升沿时，数据就会被移动，无论位是零还是一，都会被移动到 Q 输出和 Q 条输出。

Now, what about the setup and hold times? The setup time describes the duration, how long before a rising edge, a rising clock edge occurs, that a stable signal needs to be present at the input.

现在，建立时间和保持时间如何？设置时间描述持续时间，即上升沿、上升时钟沿出现之前的持续时间，输入端需要出现稳定信号。

And then again, we have the propagation delay and the propagation delay is just the time, how long it takes from here when the rising edge occurs until the D value is actually forwarded to Q.

再一次，我们有传播延迟，传播延迟就是时间，从这里出现上升沿到 D 值实际转发到 Q 需要多长时间。